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A memory chip has 8 data lines and 9 address lines. How many bytes can be stored on it?

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Posted on Jul 18, 2013

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Why there is 1024 bites in 1kilo bite... ?


because it is derived from binary base system and the data in the memory chip is either 0 or 1 for each bit. The memory is actually bytes this depends on the data bus used 8 bits = 1 byte on an 8 bit data bus. 16 bits - 1 byte on a 16 bit memory data bus.
each lot of bits being bytes sits at an address. So 1 kilo byte of memory is stored in 1024 memory addresses. this uses 10 address lines. If you add one more address line 2^11 you get 2048 memory stores . As the 11 th bit can be 1 or 0 but allows access to another 1024 memory addresses.

  • 2 ^0 =1
  • 2^1 =2
  • 2^2 = 4
  • 2^3 = 8
  • 2^4 = 16
  • 2^5 =32
  • 2^6 = 64
  • 2^7 =128
  • 2^8 =256
  • 2^9 =512
  • 2^10 = 1024 = 1 kb

Feb 17, 2016 | Cars & Trucks

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How does ram works?


RAM is an acronym for Random Access Memory, which is the memory your computer uses to hold your operating system (such as Windows 7), your applications, and working data while the computer is turned ON. These are copied from the hard drive to RAM when you turn on the computer or run an application. When power is turned OFF, all the information in RAM is gone (it is not saved). Memory in RAM is like a matrix. Address lines on the memory chip point to a single memory address at a time, where a word (8, 16, 32, or 64 bits wide) of data is stored. When power is first applied, all memory locations store zero or undetermined values. RAM is working memory or scratch-pad memory that is used for temporary storage. Permanent storage requires either EPROM, EEPROM, Flash, Battery-backed RAM or a hard drive.

See this link:
http://www.ehow.com/how-does_4899593_ram-work-computer.html

Oct 31, 2013 | Computers & Internet

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What ram for


RAM is a type of computer memory accessed randomly during hard drive processes.

A computer's RAM is considered "random" because any byte of memory can be accessed without processing previous bytes.


Purpose of RAM


RAM is used to load and run programs or applications on a computer's operating system. More RAM means more applications and programs can be run simultaneously.


SRAM


Static Random Access Memory, or SRAM, stores data on a computer in a static method, meaning the data stays the same with power being supplied to the memory chip. SRAM is the faster RAM when compared with DRAM.


DRAM


Dynamic Random Access Memory, or DRAM, is a type of memory used in personal home computers. This type of memory must have an electrical current to refresh. DRAM is used more commonly because it's less expensive to manufacturer and install in chips.


EDO RAM


Extended Data Output, or EDO, is a new type of DRAM chip that uses technology to add 10 to 15 percent more speed than normal. A computer that uses EDO technology must meet the chip requirements or the EDO will not be recognized.


FPM


Fast Page Mode, or FPM, is a RAM speed enhancement that uses rows of bits selected in columns and rows of the memory.

FPM is used in EDO RAM.




Nov 02, 2012 | Computers & Internet

1 Answer

How to programme an eprom


There are three special "Enable" pins on the EEPROM: CE (Chip Enable), OE (Output Enable), and WE (Write Enable). CE simply activates the chip (if CE is not enabled, the EEPROM will do nothing). OE makes the chip output a byte, and WE makes the chip program a byte into itself. When you are programming an EEPROM, you want to keep CE enabled the whole time, so tie CE low. (Because all three of these Enable signals are active-low; At least, they are on the 2865.) You also want to keep OE disabled the entire time, because you are not having the EEPROM output any bytes; Rather, you are programming bytes into it, so leave OE disabled: If it is active-low, tie it high to disable it. That leaves WE; Leave WE disabled for now.

The next thing you need to do is turn your EEPROM on. Connect its power pins to a power supply. (For the 2865 chip, that would be pins 14 and 28.)

The biggest step is to actually program the byte. First, configure the EEPROM's address and data buses to indicate the byte you would like to store, and the address you want to store it in. For example, to store the value 80 in the very first byte of the EEPROM (which is address 0), you'd tie all the address bus pins low (which means logical zero), so the address is set to 0. Then you'd set the data bus pins to the binary representation of 80, which is 01010000. Remember that bit numbers are read from right to left, not from left to right, so in this example, the first four data bus pins should be 0. (The second data bus pin should NOT be 1; Only the fifth and seventh will be 1.)

Once you have set up the address and data buses, the only thing left to do is cycle the WE pin to actually write the byte. Send WE low for a moment (assuming it is active-low), then put it high again. If the EEPROM is working properly, you have now stored your byte, and you can later examine it with OE. On the 2865 (and many other EEPROMs), there is a READY/BUSY pin, which is an output from the EEPROM which indicates when the chip has finished writing to itself and is ready to accept more input


Performance Chip

May 24, 2012 | HP Compaq Presario CQ61420us Notebook

2 Answers

The PC does not start.Only it beeps and a red light blinks,also fen is not working.


here are some of the basic codes, depending on which BIOS you have...

Also you do not indicate which fan? I would guess you mean the main Power Supply (PS)? In which case it could just be you need to replace the PS.

Here is a link to some other codes as well...
http://www.computerhope.com/beep.htm

AMI BIOS ERROR BEEP CODES
  • 1 Beep - Memory Refresh Failure (check memory)
  • 2 Beeps - Memory Parity Error in first 64KB block (check memory)
  • 3 Beeps - Memory Read/Write Error in first 64KB block (check memory)
  • 4 Beeps - Motherboard timer not functioning (possible motherboard replacement)
  • 5 Beeps - Processor Error (may need replacement Processor)
  • 6 Beeps - Gate A20/keyboard controller failure (possible motherboard replacement)
  • 7 Beeps - Processor Exception Interrupt Error (may need replacement Processor)
  • 8 Beeps - Display Memory Read/Write Failure (reseat or replace video card)
  • 9 Beeps - ROM checksum Error (replace BIOS chip or motherboard)
  • 10 Beeps - CMOS shutdown Read/Write error (possible motherboard replacement)
  • 11 Beeps - Bad Cache Memory - test failed (replace cache memory)

Phoenix BIOS ERROR BEEP CODES
Phoenix BIOS beep codes are a series of beeps separated by a pause, for example:
beep --- beep beep --- beep --- beep beep would be 1-2-1-2
  • 1-1-4-1 - Cache Error (level 2)
  • 1-2-2-3 - BIOS ROM Checksum
  • 1-3-1-1 - DRAM Refresh Test
  • 1-3-1-3 - Keyboard controller test
  • 1-3-4-1 - RAM Failure on address line xxxx (check memory)
  • 1-3-4-3 - RAM Failure on data bits xxxx of low byte of memory bus
  • 1-4-1-1 - RAM Failure on data bits xxxx of high byte of memory bus
  • 2-1-2-3 - ROM copyright notice
  • 2-2-3-1 - Test for unexpected interrupts
I hope this helps.

Mar 29, 2011 | HP Computers & Internet

1 Answer

Sir i write a cd i get this error somu 4C85-1000-0805-6481-407K-8KE9-**** Windows XP 6.0 IA32 WinAspi: - NT-SPTI used Nero Version: 7.10.1.0 Internal Version: 7, 10, 1, 0 (Nero Express) Recorder: ...


turn off buffer underrun protect in neros settings. It gives back the wrong info to nero causing it to crash. Contact nero about the issue. there may be a patch on the nero site to fix it.

Aug 30, 2009 | Acer Aspire 4720 Notebook

1 Answer

Beep codes


1 Long Beep: Memory problem
Explanation: There is a failure of some sort related to the system memory.
Diagnosis: The first bank of memory probably has a failure of some sort; this is usually just a physical problem such as an incorrectly inserted module, but may also mean a bad memory chip in a module. It is possible that there is a failure related to the motherboard or a system device as well.

Phoenix BIOS ERROR BEEP CODES
Phoenix BIOS beep codes are a series of beeps separated by a pause, for example:
beep --- beep beep --- beep --- beep beep would be 1-2-1-2
  • 1-1-4-1 - Cache Error (level 2)
  • 1-2-2-3 - BIOS ROM Checksum
  • 1-3-1-1 - DRAM Refresh Test
  • 1-3-1-3 - Keyboard controller test
  • 1-3-4-1 - RAM Failure on address line xxxx (check memory)
  • 1-3-4-3 - RAM Failure on data bits xxxx of low byte of memory bus
  • 1-4-1-1 - RAM Failure on data bits xxxx of high byte of memory bus
  • 2-1-2-3 - ROM copyright notice
  • 2-2-3-1 - Test for unexpected interrupts

May 14, 2009 | AOpen AX34-U Motherboard

2 Answers

Memory


According to your motherboard specs.
2 x 184-pin DIMM sockets support two 2.5V DDR SDRAMs (DDR400/333/266) ecs_buttom_03.gif Maximum: 2GBYou can use up to PC3200 that's the fastest speed it will read...

Feb 03, 2009 | PC Chips MB PCCHIPS M863G V5.1C w/XP2400+...

1 Answer

Acer Veriton 5600G Front Side Bus settings/jumpers


Hi Gerry,

The understanding of how this works will require some study on your part. This is because you would not have enough basic knowledge to understand any short answers, that someone might give.

Here are some resources for you to read so you will understand this subject.

http://computer.howstuffworks.com/motherboard4.htm

http://www.directron.com/fsbguide.html

http://en.wikipedia.org/wiki/Front_side_bus

I hope you will find the answers you are looking for here.
Good luck.

Oct 24, 2008 | Acer Veriton 5600G PC Desktop

1 Answer

Pioneer bus cable wiring


You asked for it...
..it's a little complicated.

The pioneer IP bus uses a 2 wire differential signal for communication.
An equal level on both lines is a logical low while a high is encoded as a voltage difference of some 100mV.
I think a CANbus tranceiver should work here.
The data transfer is initiated by either the cd changer or the radio.The initiator generates a high pulse ( ca. 170us ) and a following low pulse ( ca 20us ).
Then the data transfer starts, a 1 is encoded as a high-low sequence with a duration of ap. 20us for both levels and a 0 consists of a 33us high and a 7us low pulse.
The data is now transfered in bytes with MSB first, the 8th bit is an odd parity bit.At the end of the 3rd and all following Bytes there is an additional bit inserted after the parity where the receiver acknowledges the transfer.
This is done by holding the data lines in a high state after the initiator sets them low.If this ack is missing the transfer is stopped.
The timings may vary because the real data is encoded in the pulse to space length relation.
The first 3Bytes seem to be some kind of device address.The changer I used transfered a 0x88,0x68,0x00 here while the radio sended 0x88,0x08,0x06.
The next 4 bits were always high. After that a size byte and then size bytes were transfered. The last byte in the transfer is a checksum generated adding the values of all data beginning with the 4bit sequence ( = 0x0F ).
In the following part I only will write the raw data excluding size and cheksum field.
Each command transfered was first answered by some acknowledge packet consisting of a single 0xA1.
(which looks like: 0x88 0x08 0x06 0xF 0x02 0xA1 0xB2 -> 0xB0 is the checksum ).
For now I just figured out some very basic things like the fields where time, track and disc number are encoded and also some
key codes the radio sends. There are many more fields in the packets where i still don't know the meaning of.
(I just got the radio from a friend for some days and so I couldn't do so much more on it ... however .. if somebody is intrested in some
more information and is wiling giving me a radio and a changer for some weeks I'll try to do some more .... )
I have also designed a small circuit using a AT90S2313 controller which can be used for logging the transfer through the pc serial port and also
to send commands.
The following packet sended by the changer contained the time disc and track information.
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Info command modus mcd disc min sec track cdt Data 0x61 0x10 0x06 0x01 0x20 0x04 0x16 0x01 0x06 0x01 0x00 0x00 0x01 0x00 0x3F 0x00 0x00 0x00 0xC0 0x48 modus:
Value 0x02 0x07 0x08 0x10 0x11 0x13 0x14 0x15 0x16 Info ready track blink pause ready and disc blink disc blink load and disc blink eject and disc blink load eject cdt: bit0: (1:cdtext),(0:normal)
The text information was encoded within this packet
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13-22 Info command modus disc track text seqence number text Data 0x61 0x10 0x06 0x01 0x20 0x04 0x38 0x09 0x00 0x06 0x00 0x00 0x00 0x00
Recommend link: Vitaliy's Page @ http://www.vitat.spb.ru/ with IP bus interface on AVR basis and more IP bus informations
Some transfer log files are available.

Jul 20, 2008 | Car Audio & Video

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